timing clock
英 [ˈtaɪmɪŋ klɒk]
美 [ˈtaɪmɪŋ klɑːk]
网络 定时时钟; 时序; 定时钟; 时脉; 系统时钟
双语例句
- To ensure timing requirement on digital integrated circuits, clock tree synthesis is very important on ASIC backend physical layout design.
时钟树综合在芯片设计后端物理设计过程中，对于保证数字集成电路的时序是非常重要的。 - If the bus incorporates a robust timing margin, small adjustments in the clock timing should produce no errors.
如果总线有充足的时间间隙，时钟时间上很小的调整不会产生错误。 - Low Loss SAW Filters for Optical Fiber Timing Clock Recovery
光纤定时恢复器用声表面波低损耗滤波器 - Synchronization of OFDM include timing synchronization and carrier synchronization, and timing synchronization also include symbol synchronization and clock synchronization.
OFDM系统同步包括定时同步和载波同步，其中定时同步又分为符号同步和抽样同步。本文主要是研究定时同步，而载波同步只是简单的讨论，因为在这项目中这是另有负责人。 - Aim To study the influence of the acceleration and the joggling factor between the pallet and the escape wheels on the timing characteristics of the clock mechanisms with unturned escapement.
目的研究起动加速度a0和卡摆与擒纵轮间的啮合传动常数p对钟表机构走时特性的影响； - Because both of them contain different frequency spectrum, their timing clock obtaining systems are different.
由于两者频谱成分不同，其定时时钟提取方式则不同。 - By reasonably using the special resources in FPGA, such as DCMs ( Digital Clock Manager) and BUFGMUXs ( global clock MUX buffer) and manually building up a proper clock circuit, the interference to timing caused by clock skew is mostly reduced.
通过合理使用DCM（数字时钟管理单元）和BUFG-MUX（全局时钟选择缓冲器）等FPGA的特殊资源，手动搭建时钟电路，可以尽可能地减少时钟偏差对电路时序的影响。 - Methods The mathematics model and dynamic simulation software-WORKING MODEL 3D were used to build virtual prototype and to simulate the timing characteristics of the clock mechanisms with the unturned escapement in actual environments.
方法把数学模型和动力学仿真软件相结合，模拟真实条件，研究无返回力矩钟表机构的延时特性； - At last, a new timing method is introduced in this paper, it can timing a high-frequency signal with a low-frequency clock. A realization scheme is presented accordingly.
最后，本文还提出了一种新的计时方法，可以用低频计时时钟测量高频信号，并给出了一种用PLL实现的方案。 - A timing calendar clock designed based on the minimum system of chip calculator is introduced.
本篇是用单片机最小系统实现的可定时日历时钟。 - Timing Realtime Control Systems with Multimedia Clock
多媒体时钟解决实时控制系统的定时 - ATM supports transparent data transport, which brings distortion of timing information, while clock synchro-nization is the key point of ATM CES.
ATM技术很好地解决了数据的透明传送问题，但定时信息在ATM网中的传递透明性由于统计复用而受到损害，而时钟同步是电路仿真业务的关键问题。 - This paper combines with the requirement of practical engineering tasks. The research field of this paper relates to the following topics: · the design and optimize technology of clock distribution network; · the analysis and modeling of the timing characteristics of clock distribution network s;
本文结合实际的工程任务需求，重点研究了时钟网络的设计与优化技术、时钟网络时序特性的分析与建模技术； - In integrated communication equipment, timing and synchronization of clock circuit and digital transmission are combined tightly. It directly influences communication quality.
在综合通信设备中，时钟电路与数字传输中的定时及同步密不可分，它直接影响着通信质量的好坏。 - Following the introduction of the basic principle of OFDM, some nonideal effects on the performance of OFDM systems are discussed, such as carrier frequency offset, symbol timing offset and sampling clock deviation.
本文在简要介绍了OFDM的基本原理、关键技术的基础上，针对同步问题进行了深入研究。首先分析了同步偏差中的频率偏差、符号定时偏差及采样时钟偏差对系统性能的影响。 - This article analyses the timing characteristics of the G. 813 clock in detail.
文中对G.813从钟的定时特性作了详尽分析。 - Timing Clock Obtaining of NRZ Code and RZ Code In Optical Digital Communications
光纤数字通信中NRZ与RZ码序列的定时时钟提取 - High accuracy timing calendar clock
高精度可定时日历钟 - The Design and Emulate Study of Timing Sprinkler Apparatus Controlled by Alarm Clock
钟控定时喷灌器的设计与仿真研究 - This thesis analyzes some influences on the performances of OFDM digital communications, which include carrier frequency offset, symbol timing offset and sampling clock offset.
分析了载波频率偏差、符号定时偏差和样值频率偏差对OFDM系统性能的影响。 - Then we proposed an improved method, as for timing, it replaces system clock with TSC register, to eliminate clock errors; by modifying system kernel, it removes the time-stamping place from application to network driver to eliminate location errors.
提出一种改进的时延测量方法，以TSC寄存器计数取代系统时钟计时，减少了测量的时钟误差；修改系统内核，将时间戳记录位置由应用程序转移到网卡驱动，减少了测量的位置误差。 - After static timing analysis, FPGA system still have sufficient timing margin in the corresponding clock frequency when running sending and receiving parts.
进行静态时序分析后，FPGA系统中发送部分和接收部分运行在相应时钟频率下具有足够的时序余度。 - Then PTN networking and planning techniques are analyzed such as networking strategy, network management solution, VLAN and IP address allocation, quality of service issues, and timing clock solutions.
然后分析给出了PTN组网和规划技术，包括组网策略、网管规划、VLAN及IP地址规划、业务及服务质量规划和时钟同步规划等。 - As the key part of a timing driven design, clock tree synthesis and optimization is very special in a hierachical design and tool should calculate the actual clock network delays after the clock tree is built instead of using ideal clock.
作为时序设计的核心，时钟树的综合和优化在层次化流程中有其需要特别设计的地方，而时钟树综合之后要使用真实的时钟而非理性时钟来进行时序分析。 - In this thesis, through the physical design of the multi-level filter based mini-object infrared image processing, floor-planning of the design, power analysis, parasitics abstract, timing optimization, clock tree synthesis and physical verification are discussed in detail.
本文通过红外图像小目标识别多级滤波器的物理设计，对芯片的布局布线，功耗分析，寄生参数提取，时序优化，时钟树综合，物理验证等方面做了详细的描述。 - Simply introduced the base flow for Clock Tree Synthesis, and described the file of timing constrains, and then introduced the analysis for skew and timing after Clock Tree Synthesis in detail.
简要介绍了时钟树综合的基本流程，并对时序文件的内容作了简要的描述。然后对时钟树综合后的时钟偏差和时序的分析做了详细的阐述。 - Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and ( 216-1).
每一个集成异步通信器件包括一个可编程的波特率发生器，它能够对输入时钟进行1～216-1的分频。 - Phase locked loop ( PLL) and the delay phase locked loop ( DLL) are the most important part of the modern electronic equipment, and be widely used in the timing circuit and clock synthesizer circuit.
锁相环（PLL）和延时锁相环（DLL）是现代电子设备中最重要的组成部分之一，通常被用于时序电路和时钟产生电路中。 - This paper focuses on the chip in the actual design of some specific problems encountered, such as a more accurate static timing analysis, clock crosstalk, power distribution, and substrate leakage, short channel effects and so on.
这里主要讨论在实际设计芯片中所遇到的一些具体问题，诸如更准确的静态时序分析，时钟串扰，电源分布，以及衬底漏电，短沟道效应等。 - The dynamic errors are mainly timing error, clock jitter, finite output impedance, output variation effect and nonlinear switching transient.
动态误差主要有时序误差、时钟抖动、有限输出阻抗、输出波动效应、开关瞬态非线性等。